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Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* 2 LVCMOS / LVTTL outputs * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency: 350MHz (typical) * Output skew: 20ps (maximum) * Part-to-part skew: 600ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V operating supply * -40C to 85C ambient operating temperature * Lead-Free package available * Pin-to-pin compatible with MC100EPT26
GENERAL DESCRIPTION
The ICS83026I is a low skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS.The differential input can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate to two single-ended LVCMOS/LVTTL outputs with a maximum output skew of 20ps. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
ICS
BLOCK DIAGRAM
Q0 CLK nCLK Q1
PIN ASSIGNMENT
nc CLK nCLK nc 1 2 3 4 8 7 6 5 VDD Q0 Q1 GND
ICS83026I
8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View
83026AMI
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Type Unused Input Input Power Output Output Power Pullup Description No connect. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 4 2 3 5 6 7 8 Name nc CLK nCLK GND Q1 Q0 VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 Test Conditions Minimum Typical 4 VDD = 3.6V 23 51 51 7 12 Maximum Units pF pF K K
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VDD IDD Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 35 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum 2.6 0.5 Typical Maximum Units V V
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VIN = VDD = 3.6V VIN = VDD = 3.6V VIN = 0V, VDD = 3.6V VIN = 0V, VDD = 3.6V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Test Conditions 350MHz Minimum 1.7 Typical 350 2.1 5 0.8V to 2V 150 300 2.5 20 600 450 60 Maximum Units MHz ns ps ps ps %
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay, NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time
tsk(o) tsk(pp)
tR / tF
odc Output Duty Cycle 40 50 All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V0.15V
VDD
V DD
SCOPE
Qx
nCLK
V
PP
LVCMOS
GND
Cross Points
V
CMR
CLK
-1.65V0.15V
GND
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
V
V
DDO
DDO
Qx
2
Qx
2
PART 2
V
DDO
V
DDO
Qy
2 tsk(o)
Qy
2 tsk(pp)
OUTPUT SKEW
nCLK CLK
PART-TO-PART SKEW
80% 20%
tR
80% 20% tF
Q0, Q1
VDDO 2 t
Clock Outputs
PD
PROPAGATION DELAY
V
OUTPUT RISE/FALL TIME
DDO
Q0, Q1
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
83026AMI
BY
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7
REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83026I is: 416
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FOR
PACKAGE OUTLINE - SUFFIX M
8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Marking 83026AMI 83026AMI 83026AIL 83026AIL Package 8 Lead SOIC 8 Lead SOIC on Tape and Reel 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC on Tape and Reel Count 96 per tube 2500 96 per tube 2500 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83026AMI ICS83026AMIT ICS83026AMILF ICS83026AMILFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83026AMI
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REV. B NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS83026I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Revised General Description. Added Lead-Free bullet to Features section. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical and added 5 min. & 12 max. to ROUT row. Added Application Information section. Added Lead-Free P/N to Ordering Information table. Date 8/9/02
Rev A
Table
Page 1 1
T2 B T7
2 6-7 11
11/9/04
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